1. Field of the Invention
The present invention relates to a memory system and related method, and more particularly, to a memory system capable of reducing writing error occurrences effectively to enhance writing protection and related method.
2. Description of the Prior Art
A memory device is an essential part of an electronic product. The memory device is usually utilized for storing digital data and programs to be accessed by a processor. Now, many electronic products can offer multiple functions, such as multimedia, mobile, and network functions, each of which demands more memory allocation for its application.
In general, memory is classified into two types: one time programmable memory and multi-time programmable memory. A one time programmable memory, such as a read only memory (ROM), can only be programmed once. As soon as data is written into the one time programmable memory, the one time programmable memory can not be erased and rewritten to update the data. A multi-time programmable memory, such as a flash memory, can be written, erased and rewritten many times.
Although the multi-time programmable memory provides excellent convenience of use, the multi-time programmable memory may experience error occurrences. For example, the data stored in the memory may be destroyed due to an instable power supply, instable control signal, or an unexpected power problem in the instant that power is turned on or off. In other words, part or all of data stored in the memory may be overwritten or erased wrongly, causing permanent damage. Therefore, the data stored in the memory may be corrupted or incomplete, and therefore nonfunctional. Also, if the data stored in the memory is related to system data, such as a basic input output system (BIOS) code or an embedded controller (EC) code, the computer system will fail to perform normal operations.
Therefore, for preventing the data stored in the memory device from being deleted or overwritten by unexpected data accidentally, the prior art usually adopts a writing protection scheme for the memory device by using a software or hardware design for protecting the data. For example, the prior art may set a writing protection period for the memory device by using software configuration, and utilize commands to limit any writing or erasing operation in the memory device during the writing protection period. As a result, the data stored in the memory device will not be varied if the memory device encounters the above-mentioned external factors during the writing protection period. In addition, the prior art can also use hardware design to provide the writing protection scheme. For example, the prior art uses the EC to restrict the writing process of the memory device through general purpose input output (GPIO) pins, and therefore, the memory device can avoid error writing or error erasing occurrences during the writing protection period. However, the writing protection schemes designed with software or hardware of the prior art only prevent erroneous writing to the memory device during the writing protection period. Various data writing processes may require various processing times, but an allowable data writing period is often a fixed length of time in the prior art. The memory device may also suffer the erroneous writing during the data writing period when normal data have been written to the memory device. For example, please refer to FIG. 1, which is a schematic diagram illustrating the data writing operating according to the prior art. Suppose a period X (timing point A to timing point B) and a period Z (timing point C to timing point D) are, respectively, writing protection periods, and a period Y (timing point B to timing point C) is a data writing period. This means any data writing or erasing process can be performed in the memory during the period Y. The data type and the amount of data written to the memory device during the period Y are uncertain for each data writing process, but the period Y is often an interval having a fixed length of time in the prior art. In such a situation, as shown in FIG. 1, the required processing time of a data writing operation may be shorter than the length of the period Y. Suppose a data writing process performed in the memory device begins at the timing point B, and all expected data writing operations have been finished by the timing point C′. In other words, a blank period (timing point C′ to timing point C) exists, during which no data writing processing is applied. When the above-mentioned unexpected external factors occur during the blank period, the unexpected data will be written to the memory device, causing an erroneous writing situation. For example, an unstable power supply may cause an unexpected signal variation during the blank period, which the memory device will take to be a normal data signal, causing an erroneous writing situation. In short, for a memory device, an unnecessary blank time may remain in the data writing period in the prior art, which may easily lead to erroneous data writing.